
COMMERCIALTEMPERATURERANGE
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
23
Symbol
Parameter
Min.
Typ.
Max.
Unit
tPZL
Output Enable Delay (All Outputs)(1)
0—
10
μs
tPZH
tPLZ
Output Disable Delay (All Outputs)(1)
0—
10
μs
tPHZ
tSTABLE
All Clock Stabilization from Power-Up(2)
——
3
ms
tSPREAD
Setting Period for Spread Selection Change(2,3)
——
3
ms
MISCELLANEOUS AC TIMING REQUIREMENTS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C
NOTES:
1.
These specifications apply to the LVDS and SMBus pins. These pins must be tri-stated when PWRDWN is asserted. LVDS is driven differential when PWRDWN is de-asserted unless
it is disabled.
2.
The time specified is from when VDD achieves its nominal operating level (typical condition VDD = 3.3V) and PWRDWN is de-asserted until the frequency output is stable and operating
within specification.
3.
The time specified is measured from the spread selection change or output frequency change until the LVDS clock is operating at the new spread modulation and frequency.
If there is another change in spread selection or output frequency during the tSPREAD settling period, then the settling period start resets to the most recent change in spread selection
and output frequency.